The present invention relates to manufacturing methods of semiconductor devices, and more particularly, to a manufacturing method of a semiconductor device with a multi-layered wiring structure.
Semiconductor devices have been increasingly microfabricated. For example, wirings of the semiconductor device have been downsized to the minimum width of about 100 nm or less. In multi-layered wiring technology, the influences on the device characteristics due to RC (resistance-capacitance) delay have been a more serious problem. A Cu (copper)/low dielectric constant film (Low-k film) wiring technology has been developed as measures against the RC delay. Low-k materials with a value of k of not less than 2.5 nor more than 3.1, such as SiOCH (carbon-doped SiO2), have been put into practical use. The Low-k materials are required to have a lower dielectric constant for the next generation, and the next generation. For this reason, porous Low-k materials or the like having holes in a low dielectric constant film are developed.
Such Low-k materials, however, have low resistance to process using chemicals or plasma, for example, etching or ashing. When the Low-k material is subjected to etching or ashing, the Low-k material tends to become deteriorated. That is, the Low-k material possibly has its dielectric constant increased, or possibly degrades the film.
The Low-k film has the low resistance to the process using the chemicals or plasma, which makes it difficult to control a pattern of the wiring formed by etching the Low-k film. For example, in order to control the depth (thickness) of the wiring, it is difficult to etch the Low-k film only in a desired depth with high accuracy. As a result, variations in thickness of the formed wiring disadvantageously tend to occur, which leads to variations in electrical resistance of the wiring, and thus in amount of current flowing through the wiring. Such a phenomenon reduces the reliability of the semiconductor device.
Further, when performing the process (asking) for removing a resist used for forming the wiring trench pattern, the inside of the wiring trench pattern may be damaged to increase the RC delay of the wiring together with an increase in dielectric constant, and to degrade a withstand voltage between the wirings due to occurrence of leak current. Thus, the reliability of the semiconductor device is possibly degraded.
The following manufacturing methods are conventionally disclosed as technique for forming a multi-layered wiring using the above low dielectric constant film.
For example, Japanese Unexamined Patent Publication No. 2009-4408 (Patent Document 1) discloses a method for forming both a wiring trench pattern in a low dielectric constant film, and a via pattern (via hole pattern) for electrically coupling the trench pattern to a wiring as a lower layer. When forming the wiring trench pattern by etching after previously forming the via hole pattern, a film generated by the etching and a damaged layer which are formed over an inner wall of the pattern are removed by plasma using a predetermined gas. In this way, the reliability of the wiring formed in the pattern is improved.
For example, Japanese Unexamined Patent Publication No. 2007-335450 (Patent Document 2) discloses a method for forming a dual damascene structure using a multi-layered resist. Japanese Unexamined Patent Publication No. 2006-32864 (Patent Document 3) discloses a method for forming a dual damascene structure using a multi-layered mask. Japanese Unexamined Patent Publication No. 2008-218959 (Patent Document 4) discloses an etching method which can perform etching into a good shape of process without damaging a carbon film with fluorine added thereto as an interlayer insulating film having a low dielectric constant. Japanese Unexamined Patent Publication No. 2005-38967 (Patent Document 5) discloses a method for forming a contact layer using a SiC film or a SiO2 cap film.